Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation.
The terms “die”, “semiconductor chip”, and “semiconductor die” are used interchangeably throughout this specification. The term wafer is used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the circuit structure.
FIGS. 1A through 1E show schematic, cross-sectional diagrams of a typical method for fabricating a wafer level package having a redistribution layer (RDL).
As shown in FIG. 1A, a wafer 100 is prepared. The wafer 100 may include a plurality of semiconductor device structures (not shown) formed according to known processes. An RDL layer is then formed according to known processes on the wafer 100. In FIGS. 1A-1E, the RDL is symbolically illustrated as the group of layers 102, 104, and 106. The RDL is typically defined by the addition of metal and dielectric layers onto the surface of the wafer to re-route the I/O layout into a looser pitch footprint. Such redistribution typically includes thin film polymers such as BCB, PI or other organic polymers and metallization such as Al or Cu to reroute the peripheral pads to an area array configuration. Layers 102 and 106 represent dielectric layers and layer 104 represents metallic features. Layers 102, 104, and 106 collectively represent dielectric and metal layers formed to allow for electrical communication from the wafer 100 to solder bumps or solder balls 108 shown in FIG. 1E. Solder balls 108 are formed on the RDL for further connection. As also shown in FIG. 1E, a dicing or sawing process may be performed along kerf regions of the wafer to separate individual wafer level dies from one another.
In wafer level packaging, the wafer and the dies are susceptible to warping due to coefficient of thermal expansion (CTE) mismatch. It is known that wafer warpage continues to be a concern. Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer. Warpage issue is serious especially in a large sized wafer and has raised an obstacle to a wafer level semiconductor packaging process that requires fine-pitch RDL process.
The present disclosure provides novel improved packaging methods resulting in reduced warpage or other defects.